This invention relates to FET buffer amplifier circuits, and more particularly to FET buffer amplifier circuits for use in track and hold applications.
A common prior art approach is shown in FIG. 1 and is commonly known as a "totem pole" configuration. The circuit consists of FET transistors 10 and 12. The gate and source of transistor 10 are coupled together, and the drain of transistor 10 is coupled to the drain of transistor 12. Transistor 10 develops a constant current, I.sub.DSS, which flows through transistor 12. Therefore, the resultant voltage drop between the input terminal 14, the gate of transistor 12, and the output terminal 16, the source of transistor 12, is equivalent to the voltage drop across the gate to source of transistor 10, i.e. zero.
The basic totem pole configuration is not well suited to track and hold operations in which a hold capacitor gated by a sampling bridge (not shown) is coupled to the input terminal 14. The totem pole configuration has an undesirable negative input impedance. Stated another way, transistor 12 usually drives some load capacitance as well as the gate to drain capacitance of transistor 10. The result is that the source voltage of transistor 12 lags the gate voltage of transistor 12. (negative input impedance) The effect in track and hold circuits is that the source voltage continues to change after the sampling bridge is switched off. This change in gate to source voltage causes charge to be transferred from the gate to source capacitor to the hold capacitor, introducing a frequency dependent error in the held voltage.
Although the basic configuration has often been modified to improve supply rejection, noise, thermal distortion, offset voltage, or input impedance, the modification is usually at the expense of one of the other aspects of performance. For example, FIG. 2 shows a basic totem pole configuration which has been modified to improve power supply rejection and thermal distortion. This prior art approach includes transistors 18 and 20 in a common base configuration to improve the output impedance of transistors 10 and 12. While this prior art configuration has some improvement in performance, power dissipation is increased. Also, for the same amount of output voltage swing at output terminal 16, larger supply voltages are required.
What is desired is an FET buffer amplifier circuit having reduced lag in the source voltage suitable for track and hold applications, low thermal distortion, low offset voltage, high power supply rejection, and low noise without increased power dissipation or the need for increased operating supply voltages.